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1 em681fv16b family low power , 512kx16 sram product family row select i/o circuit column select data cont data cont pre-charge circuit memory array 2048 x 4096 a1 a2 a3 a4 a5 a6 a7 a0 a8 a9 a11 we oe ub lb cs dq0 ~ dq7 dq8 ~ dq15 v cc v ss control logic functional block diagram a10 features ? process technology : 0.15 m full cmos ? organization : 512k x 16 bit ? power supply voltage : 2.7v ~ 3.6v ? low data retention voltage : 1.5v(min.) ? three state output and ttl compatible ? package type : 48-fpbga, 44-tsop2 general description the as6c8016a is fabricated by alliance ' s advanced full cmos process technology. the families suppor t industrial temperature range and chip scale package for user flexibility of system design. the families also support low data retention voltage for battery back- up operation with low data retention current. a12 a13 a14 a15 a16 a17 a18 august 2010 512k x 16 bit low power cmos sram as6c8016a product family product family operating temperature vcc range speed power dissipation pkg type standby (i sb1 , typ.) operating (i cc1 .max.) as6c8016a industrial (-40 ~ 85 o c) 2.7 ~ 3.6 v 55 ns 2 a 1) 4 ma kgd AS6C8016A-55BIN 48-fpbga as6c8016a-55zin 44-tsop2 1 . typical values are measured at vcc=3.3v, t a =25 o c and not 100% tested.
2 em681fv16b family low power, 512kx16 sram pin description name function name function cs chip select input v cc power supply oe output enable input v ss ground we write enable input ub upper byte (dq8~dq15) a0~a18 address inputs lb lower byte (dq0~dq7) dq0~dq15 data inputs/outputs nc no connection pin configurations fpbga-48 : top view(ball down) 123456 a lb oe a0 a1 a2 nc b dq8 ub a3 a4 cs dq0 c dq9 dq10 a5 a6 dq1 dq2 d v ss dq11 a17 a7 dq3 v cc e v cc dq12 nc a16 dq4 v ss f dq14 dq13 a14 a15 dq5 dq6 g dq15 nc a12 a13 we dq7 h a18a8 a9a10a11nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 a4 a3 a2 a1 a0 cs dq0 dq1 dq2 dq3 v cc v ss dq4 dq5 dq6 dq7 a5 a6 a7 oe ub lb dq15 dq14 dq13 dq12 v ss v cc dq11 dq10 dq9 dq8 44 - tsop2 17 18 19 20 21 22 28 27 26 25 24 23 we a18 a17 a16 a15 a14 a8 a9 a10 a11 a12 a13 44 - tsop2 : top view august 2010 512k x 16 bit low power cmos sram as6c8016a
3 em681fv16b family low power, 512kx16 sram absolute maximum ratings 1) parameter symbol ratings unit voltage on any pin relative to vss v in , v out -0.2 to 4.0 v voltage on vcc supply relative to vss v cc -0.2 to 4.0 v power dissipation p d 1.0 w operating temperature t a -40 to 85 o c 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent dam age to the device. functional operation should be restricted to recommended operating condition. exposure to absolute ma ximum rating conditions for exte nded periods may affect reliability. functional description cs oe we lb ub dq0~7 dq8~15 mode power h x x x x high-z high-z deselected stand by x x x h h high-z high-z deselected stand by l h h l x high-z high-z output disabled active l h h x l high-z high-z output disabled active l l h l h data out high-z lower byte read active l l h h l high-z data out upper byte read active l l h l l data out data out word read active l x l l h data in high-z lower byte write active l x l h l high-z data in upper byte write active l x l l l data in data in word write active note : x means don?t care. (must be low or high state) august 2010 512k x 16 bit low power cmos sram as6c8016a
4 em681fv16b family low power, 512kx16 sram recommended dc operating conditions 1) parameter symbol min typ max unit supply voltage v cc 2.7 3.3 3.6 v ground v ss 0 0 0 v input high voltage v ih 2.2 - v cc + 0.2 2) v input low voltage v il -0.2 3) - 0.6 v 1. ta= -40 to 85 o c, otherwise specified 2. overshoot: v cc +2.0 v in case of pulse width < 20ns 3. undershoot: -2.0 v in case of pulse width < 20ns 4. overshoot and undershoot are sampled, not 100% tested. item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/ouput capacitance c io v io =0v - 10 pf capacitance 1) (f =1mhz, t a =25 o c) 1. capacitance is sampled, not 100% tested dc and operating characteristics parameter symbol test conditions min typ max unit input leakage current i li v in =v ss to v cc -1 - 1 a output leakage current i lo cs =v ih or oe =v ih or we =v il or lb = ub =v ih v io =v ss to v cc -1 - 1 a operating power supply i cc i io =0ma, cs =v il , we =v ih, v in =v ih or v il - - 2 ma average operating current i cc1 cycle time=1 s, 100% duty, i io =0ma, cs < 0.2v, lb < 0.2v or/and ub < 0.2v, v in < 0.2v or v in > v cc -0.2v - - 4 ma i cc2 cycle time =min, i io =0ma, 100% duty, cs =v il , lb =v il or/and ub =v il , v in =v il or v ih ma 55ns - - 35 output low voltage v ol i ol = 2.1ma - - 0.4 v output high voltage v oh i oh = -1.0ma 2.4 - - v standby current (ttl) i sb cs =v ih, other inputs=v ih or v il - - 0.5 ma standby current (cmos) i sb1 cs > v cc -0.2v, other inputs = 0~v cc (typ. condition : v cc =3.3v @ 25 o c) (max. condition : v cc =3.6v @ 85 o c) lf - 2 1) 15 a 1. typical values are measured at vcc=3.3v, t a =25 o c and not 100% tested. august 2010 512k x 16 bit low power cmos sram as6c8016a
5 em681fv16b family low power, 512kx16 sram ac operating conditions test conditions ( test load and test input/output reference) input pulse level : 0.4 to 2.4v input rise and fall time : 5ns input and output reference voltage : 1.5v output load (see right) : cl 1) = 100pf+ 1 ttl(70nsec) cl 1) = 30pf + 1 ttl(45ns/55ns) 1. including scope and jig capacitance 2. r 1 =3070 , r 2 =3150 3. v tm =2.8v 4. cl = 5pf + 1 ttl (measurement with t lz , t hz , t olz , t ohz , t whz ) (v =2.7 to 3.6v, gnd = 0v, t = -40 o c to +85 o c) (v =2.7 to 3.6v, gnd = 0v, t = -40 o c to +85 o c) 55ns 70ns unit min max min max 55 - 70 - ns 45 - 60 - ns 0 - 0 - ns 45 - 60 - ns 45 - 60 - ns 45 - 55 - ns 0 - 0 - ns 0 20 0 25 ns 40 40 ns 0 - 0 - ns 5 5 - ns cl 1) v tm 3) r 1 2) r 2 2) august 2010 512k x 16 bit low power cmos sram as6c8016a read cycle cc a parameter symbol 5 5ns min max read cycle time t rc 55 - address access time t aa - 55 chip select to output t co - 55 output enable to valid output t oe - 35 ub , lb access time t ba 45 chip select to low-z output t lz 5 - ub , lb enable to low-z output t blz 5 - output enable to low-z output t olz 5 - chip disable to high-z output t hz 0 20 ub , lb disable to how-z output t bhz 0 20 output disable to high-z output t ohz 0 20 output hold from address change t oh 10 - write cycle cc a parameter symbol 5 5ns min max write cycle time t wc 55 - chip select to end of write t cw 45 - address setup time t as 0 - address valid to end of write t aw 45 - ub , lb valid to end of write t bw 45 - write pulse width t wp 45 - write recovery time t wr 0 - write to ouput high-z t whz 0 20 data to write time overlap t dw 25 data hold from write time t dh 0 - end write to output low-z t ow 5 - unit ns ns ns ns ns ns ns ns ns ns ns ns unit ns ns ns ns ns ns ns ns ns ns ns
6 em681fv16b family low power, 512kx16 sram timing waveform of read cycle(2) (we = v ih ) t rc address t aa data valid t oh previous data valid timing waveform of read cycle(1) (address controlled, cs =oe =v il , we =v ih, ub or/and lb = v il ) data out timing diagrams notes (read cycle) 1. t hz and t ohz are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given devic e and from device to device interconnection. t rc address cs ub ,lb oe data out t co t oh t ba t oe high-z t bhz t ohz data valid t olz t blz t lz t aa t hz august 2010 512k x 16 bit low power cmos sram as6c8016a
7 em681fv16b family low power, 512kx16 sram t wr (4) t wc address cs ub ,lb we data in data out t cw (2) t aw t bw t wp (1) t as (3) high-z t dw t dh high-z t ow t whz data undefined timing waveform of write cycle(1) (we controlled) data valid t wc address cs ub ,lb we data in data out t cw (2) t wr (4) t bw t wp (1) t dw t dh timing waveform of write cycle(2) (cs controlled) t as (3) high-z high-z data valid t aw august 2010 512k x 16 bit low power cmos sram as6c8016a
8 em681fv16b family low power, 512kx16 sram notes (write cycle) 1. a write occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transition when cs goes high and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end or write to the address change. t wr applied in case a write ends as cs or we going high. august 2010 512k x 16 bit low power cmos sram as6c8016a t wc address cs ub ,lb we data in data out t cw (2) t wr (4) t bw t wp (1) t dw t dh timing waveform of write cycle(3) (ub , lb controlled) high-z high-z data valid t as (3) t aw
9 em681fv16b family low power, 512kx16 sram data retention characteristics parameter symbol test condition min typ max unit v cc for data retention v dr i sb1 test condition (chip disabled) 1) 1.5 - 3.6 v data retention current i dr v cc =1.5v, i sb1 test condition (chip disabled) 1) - - 4 a chip deselect to data retention time t sdr see data retention wave form 0 - - ns operation recovery time t rdr t rc - - notes 1. see the i sb1 measurement condition of datasheet page 4. data retention wave form t sdr t rdr data retention mode cs > vcc-0.2v v cc 2.7v 2.2v v dr cs , lb / ub gnd august 2010 512k x 16 bit low power cmos sram as6c8016a max
10 em681fv16b family low power, 512kx16 sram package dimension 44 - tsop2 (0.8mm pin pitch) unit : millimeters / inches august 2010 512k x 16 bit low power cmos sram as6c8016a
11 em681fv16b family low power, 512kx16 sram 0.5 #a1 a 0.79typ. 0.25 typ. e2 0.26 e1 e a b c d e f g h 654321 b b1 0.5 c c1 b/2 c1/2 b c 48 ball fine pitch bg a (0.75mm ball pitch) bottom view top view c d y min typ max a - 0.75 - b 7.9 5 8.00 8. 05 b1 - 3.75 - c 9.9 5 10.00 10. 05 c1 - 5.25 - d 0.30 0.35 0.40 e- - 1.00 e1 - - 0.70 e2 0.20 0.25 0.30 y- - 0.08 notes. 1. bump counts : 48(8row x 6column) 2. bump pitch : (x,y)=(0.75x0.75) (typ.) 3. all tolerence are +/-0.050 unless otherwise specified. 4. typ : typical 5. y is coplanarity : 0.08(max) side view detail a a1 index mark unit: millimeters august 2010 512k x 16 bit low power cmos sram as6c8016a
12 em681fv16b family low power, 512kx16 sram memory function guide 1. memory comp onent 8. version blank--------------- mother die 2. device type a --------------- 2 nd generation 6 --------------- low power sram b --------------- 3 rd generation 7 --------------- stram c --------------- 4 th generation c --------------- cellularram d --------------- 5 th generation e --------------- 6 th generation 3. density f --------------- 7 th generation 1 --------------- 1m g --------------- 8 th generation 2 --------------- 2m 4 --------------- 4m 9. package 8 --------------- 8m blank--------------- kgd, fbga 16 --------------- 16m s --------------- 32 stsop1 32 --------------- 32m t --------------- 32 tsop1 64 --------------- 64m u --------------- 44 tsop2 28 --------------- 128m v --------------- 32 sop 4. option 10. speed 0 --------------- dual cs 45 --------------- 45ns 1 --------------- single cs 55 --------------- 55ns 60 --------------- 60ns 5. technology 70 --------------- 70ns f --------------- full cmos 85 --------------- 85ns 90 --------------- 90ns 6. operating voltage 10 --------------- 100ns t --------------- 5.0v 12 --------------- 120ns v --------------- 3.3v u --------------- 3.0v 11. power s --------------- 2.5v ll --------------- low low power r --------------- 2.0v lf --------------- low lo w power(pb-free & green) p --------------- 1.8v l --------------- low power s --------------- standard power 7. organization 8 --------------- x8 bit 16 --------------- x16 bit 32 --------------- x32 bit em x xx x x x xx x x -xx xx 1. emlsi memory 2. device type 11. power 3. density 10. speed 4. function 9. package 5. technology 8. version 6. operating voltage 7. organization august 2010 512k x 16 bit low power cmos sram as6c8016a ordering information alliance organ iza tion vcc range package operating temp speed ns as6c8016a -55zin 512k x 16 2.7 - 5.5v 44pin tsop ii industrial ~ -40 c - 85 c 55 as6c8016a -55bin 512k x 16 2.7 - 5.5v 48ball fb ga industrial ~ -40 c - 85 c 55 part numbering system as6c 8016 -55 x x n device number package option temperature range 80 = 8m z - 44pin tsop i = industrial low power sram prefix 16 = x16 access time b = 48ball tfbga (-40 to + 85 c) n = lead free rohs compliant part alliance organ iza tion vcc range package operating temp speed ns as6c8016a -55zin 512k x 16 2.7 - 3.6 v 44pin tsop ii industrial ~ -40 c - 85 c 55 as6c8016a -55bin 512k x 16 2.7 - 3.6 v 48ball fb ga industrial ~ -40 c - 85 c 55 part numbering system as6c 8016 -55 x x n device number package option temperature range 80 = 8m z - 44pin tsop i = industrial /ow power sram prefix 16 = x16 access time b = 48ball fbga (-40 to + 85 c) n = lead free rohs compliant part copyright ? alliance memory all rights reserved alliance memory, inc 5 1 taylor way, san carlos, ca 94070, usa phone: 650-610-6800 fax: 650-620-9211 www.alliancememory.com ? copyright 2007 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or registered trademarks ofalliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to thisdocument and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the datacontained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at anytime, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information inthis product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of anyproduct described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability orwarranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to inalliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance'st erms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; mask works rights,trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components inlife-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion ofalliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against allclaims arising from such use. ? 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